1. Field of the Invention
The present invention relates to a circuit for evaluating signals and in particular a circuit having a comparator with one input connected to a signal line and the other input connected to a circuit node supplying a reference potential to the comparator which is formed by a tap of an ohmic voltage divider connected to ground at one side, and an amplifier interconnected between the signal line and the comparator.
2. Description of the Prior Art
A circuit arrangement for evaluating signals such as output signals of optical measuring devices is known from U.S. Pat. No. 4,075,507 corresponding to German AS 26 08 206 wherein a measuring device is connected to one input of a comparator and which includes a voltage divider having a tap connected to the other input of the comparator. A storage capacitor is connected to the tap of the voltage divider and to the other input of the comparator so as to provide a reference voltage which has a fixed relation to the signal voltage from the measuring device in the quiescent state. The voltage divider employed in this arrangement for the formation of the reference potential is disposed between ground and the signal line, and the capacitor is connected between the reference input of the comparator and ground, so that the reference potential is determined by the charge state of the capacitor which is charged by means of the voltage divider tap. In this device it is assumed that only such signals will be present on the signal line which result in a rapid and sufficiently large signal level change so that the reference potential for conducting the signal evaluation remains substantially unchanged as a result of the relatively high charging time constant. For signals of longer duration, however, the charging of the capacitor would be influenced by the other signal lines level and the signal evaluation would thus be falsified. It is therefore provided in this conventional arrangement to switch the capacitor to an auxiliary voltage source for the evaluation of such a signal by the use of a switch driven by the comparator output signal and to thus prevent a resetting of the comparator for a long duration. Thus, a stable reference potential at the signal zero level is made available to the reference input of the comparator, however, relatively complex circuit outlay is required to maintain the circuit arrangement operational for all signal shapes and durations.